High Speed Electrical Signalling: Overview and Limitations

Improving fabrication technology enables not only the scaling of on-chip gate speeds but also the data rate of inter-chip communication interfaces. Simple low latency offchip interfaces are limited by the maximum clock frequency that can be propagated onchip. More complex serial links break this barrier, by employing high fan-in multiplexing transmitters and high fan-out de-multiplexing receivers, thus achieving bit-times on the order of an on-chip gate-delay. As technology scales, the higher signalling rates exceed the bandwidth of the external communication media. Fortunately, the increasing integration levels also enable the use of complex modulation and coding schemes to better utilize the available signal power and bandwidth for higher data rates. However, the complexity of these schemes increases the power, area, and latency overhead of the link, thus limiting their application to bandwidth-critical and wire-limited systems. With smaller feature-sizes and higher resolution requirements, the increased effect of on-chip mismatches limits both the data and clock recovery performance, posing future circuit design challenges.